In performing a digital to analog conversion utilizing switched capacitors, a discontinuity which is typically referred to as offset error may occur when transitioning between positive and negative numbers. Offset errors are caused, in part, from voltage errors associated with a digital to analog converter (DAC) structure. Such offset errors are very undesirable for DACs utilized in speech applications because offset error may introduce harmonic frequencies that drastically affect the quality of sound. Other errors associated with a DAC structure, such as gain and nonlinearity errors, are not as critical in speech applications and may be compensated otherwise.
Various codes and conversions exist in the D/A and A/D conversion art. Well known bipolar codes which represent analog signals of two polarities are sign-magnitude, two's complement, one's complement and offset binary codes. For bipolar (i.e. two polarities) applications, two's complement, one's complement and offset binary have disadvantages which produce errors when transitioning at the zero level between negative and positive numbers. In both two's complement and offset binary code, a major bit transition occurs at zero which can produce offset and linearity problems. One's complement code has an ambiguous zero because zero is represented by either all zeroes or all ones. Further, one's complement code is not as easily implemented as two's complement code. The sign-magnitude code is the only well known code in which the magnitude bits do not experience a major transition at zero. Sign-magnitude also has an ambiguous zero which typically requires additional software or hardware to resolve. However, this disadvantage is outweighed by the advantage which sign-magnitude code has over the other well-known codes at zero. Therefore, others have used code conversion circuits to convert from two's complement code to sign-magnitude code. When converting from two's complement code to sign-magnitude code, others have used software programs or a direct hardware circuit requiring multiple clock cycles.